The field of the invention is generally related to Peripheral Components Interconnect (PCI), and more specifically, to reducing the number of traces required for connecting multiple physical interfaces.
A PCI Express bus is an implementation of the Peripheral Components Interconnect (PCI) computer bus according to the set of PCI Express specifications promulgated by the PCI Special Interest Group (PCI SIG). A PCI Express bus uses existing PCI programming and software concepts, but is based on a different and much faster serial physical-layer communications protocol. Specifically, PCI Express is a network of serial interconnections extending to multiple devices in a PCI Express hierarchy which may contain PCI Express switches. The switches provide point-to-point communications between devices connected to each switch. Devices and switches operating according to the PCI Express specifications are generally referred to as ‘PCI Express devices’ and ‘PCI Express switches’ respectively.
A connection between any two PCI Express devices is referred to as a ‘link.’ A link consists of a collection of one or more lanes used for data communications between devices. Each lane is a set of two unidirectional low voltage differential signaling pairs of transmission pathways such as, for example, traces along a motherboard. Because transmitting data and receiving data are implemented using separate differential pairs, each lane allows for full-duplex serial data communication of up to five gigabits of data per second.
All devices at least support single-lane links. PCI Express devices may optionally support wider links composed of two, four, eight, twelve, sixteen, or thirty-two lanes by providing additional pins on the hardware interface of the device that plug into a PCI Express connector. A PCI Express connector is a connector manufactured according to the PCI Express specifications and may physically support connections for one, two, four, eight, twelve, sixteen, or thirty-two lanes in a manner similar to PCI Express devices. A PCI Express device may install into any PCI Express connector that physically supports the same or a greater number of lanes as the lanes physically supported by the PCI Express device. For example, a PCI Express device physically supporting eight lanes may be installed in to a PCI Express connector physically supporting eight, twelve, sixteen, or thirty-two lanes. Such an eight lane PCI Express device, however, cannot be physically installed in a one, two, or four lane PCI Express connector.
Although a PCI Express device and the PCI Express connector into which the device is installed may physically support links with up to thirty-two lanes, a PCI Express device may utilize fewer lanes for data communication than the maximum number of lanes physically supported by the device and the connector. For example, a PCI Express device may physically support eight lanes and be installed in a PCI Express connector physically supporting sixteen lanes. The eight lane PCI Express device may, however, only utilize one, two, or four of those eight lanes it supports for data communications with other PCI Express devices. The number of lanes actually utilized for the data communications link between two devices is typically the highest number of lanes mutually supported by the devices.